The present invention generally relates to electronic circuit design, and, more particularly, to a system and method for adding features to parameterized cells (pcells) used in an electronic circuit design.
Electronic design automation (EDA) tools are used extensively in very large scale integration (VLSI) circuit design for creating hierarchical designs. EDA tools facilitate breaking a complex circuit design into small and manageable sub-designs that include conventional cells. The conventional cells implement logic or other functions using various integration technologies.
EDA tools also facilitate generation of ‘parameterized cells’ (pcells), which are cells for which various parameters of their circuit components can be specified. A pcell is automatically generated by an EDA tool based on the values of its parameters. The source code of the pcell is executed by the EDA tool, which uses either modified or default parameter values to generate a customized instance of the pcell. A pcell is more flexible than a conventional cell in that different instances of the pcell may have different parameter values. For example, rather than having various cell definitions to represent transistors of different dimensions in a given design, a single pcell can take dimensions of a transistor as its parameters. Different instances of the single pcell can then have transistors of different dimensions. EDA tools also facilitate defining various features of the pcells, such as connectivity, stretch handles, abutment, pcell tiling, guard rings, taps for substrate connectivity, metal via stacks, additional layers, and so forth, as known by those of skill in the art.
It is often required to modify the features or functionality of pcells. To add new features, significant modifications and rework of the existing design layout is required, which can be a cumbersome and time consuming task. Moreover, every time a new feature is introduced in an existing design, the same rework is required. For example, in an EDA tool, if the additional feature is included as a menu based utility in the existing pcell hierarchy, the utility must be re-run every time a change is introduced in the design.
Another method of introducing a new feature is to implement it using hidden parameters (for example, in component description format (CDF). Although these parameters are hidden, they can be inadvertently accessed, which may lead to unforeseen results. Yet another method requires code-level changes in the existing pcell design. These changes cause the pcells to become bulky and complex, thereby increasing computational overhead. In addition, when the pcell codes are encrypted, for example, as in the case of third party pcell codes, features cannot be added easily due to the encryption.
Therefore, it would be advantageous to be able to easily add a feature to an existing hierarchy of pcells, eliminate rework and modifications of an existing design layout, and reduce computational overhead. It also would be advantageous to be able to easily add features to pcells with encrypted codes.